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rev 0.7 / nov. 2005 1 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash document title 2gbit (256mx8bit / 128mx 16bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. nov. 19. 2004 preliminary 0.1 jan. 20. 2005 preliminary 0.2 mar. 03. 2005 preliminary 1) add errata tcls tclh twp tals talh tds twc tr specification 0 10 25 0 10 20 50 25us relaxed value 5 15 45 5 15 25 70 27us case trc trp treh trea specification read(all) 50 20 20 30 relaxed value except for id read 50 20 20 30 id read 60 25 30 30 2) add note.4(table14) 3) add application note(power on/o ff sequence & auto sleep mode) - texts & figures are added. 4) change ac parameters case tdh before x8, x16 10 after x8 10 x16 15 1) change ac parameters case tdh before x8 10 x16 15 afer x8, x16 15 2) add tadl(=100ns) parameters 3) add muliti die concurrent operations and extended read status - texts and table are added. 4) edit table.8 5) change fbga package dimension
rev 0.7 / nov. 2005 2 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash revision history -continued- revision no. history draft date remark 0.3 apr. 01. 2005 preliminary 0.4 1) correct ac timing characristics table - errata value is eddited. - tadl(max) is changed to tadl(min) 2) chage errata - trea is deleted from the errata 3) correct operating current(typ.) - before : 10ma -> after : 15ma(3.3v) - before : 8ma -> after : 10ma(1.8v) apr. 06. 2005 preliminary 0.5 1) correct the test conditio ns (dc characteristics table) 2) change ac conditions table 3) add tww parameter ( tww = 100ns, min) - texts & figures are added. - tww is added in ac timing characteristics table. 4) edit system interface using ce don?t care figures. 5) correct address cycle map. aug. 05. 2005 preliminary 1) change errata - errata values (twp & twc) are changed tcls tclh twp tals talh tds twc tr before 5 15 45 5 15 25 70 25us after 5 15 40 5 15 25 60 27us case trc trp treh before except for id read 50 20 20 id read 60 25 30 after read (all) 60 25 30 te s t c o n di t io n s ( i cc1) test conditions ( i li, i lo ) before t rc =50ns, ce#= v il , i out =0ma vin=vout=0 to 3.6v after t rc (1.8v=60ns,3.3v=50ns) ce#= v il , i out =0ma vin=vout=0 to vcc (max) rev 0.7 / nov. 2005 3 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash revision history -continued- revision no. history draft date remark 0.6 1) change 2gb package type. - fbga package is deleted. - wsop package is changed to usop package. - figure & dimension are changed. 2) correct pkg dimension (tsop, usop pkg) 3) add trbsy (table 12) - trbsy (dummy busy time for cache read) - trbsy is 5us (typ.) 4) delete errata 5) change ac characteristics oct. 19. 2005 0.7 1) change ac characteristics nov. 04. 2005 cp before 0.050 after 0.100 trc trp treh before 60 25 30 after 60 40 30 50 25 20 trc trp treh before read id 60 40 30 data read 50 25 20 after read id 60 25 30 data read 50 25 20 rev 0.7 / nov. 2005 4 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ugxx2g2m - 1.8v device: vcc = 1.7 to 1.95v : hy27sgxx2g2m memory cell array = (2k+ 64) bytes x 64 pages x 2,048 blocks = (1k+32) words x 64 pages x 2,048 blocks page size - x8 device : (2k + 64 spare) bytes : hy27(u/s)g082g2m - x16 device: (1k + 32 spare) words : hy27(u/s)g162g2m block size - x8 device: (128k + 4k spare) bytes - x16 device: (64k + 2k spare) words page read / program - random access: 27us (max.) - sequential access: 60ns (min.) - page program time: 300us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27(u/s)g(08/16)2g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27(u/s)g(08/16)2g2m-t (lead) - hy27( u/s)g(08/16)2g2m-tp (lead free) - hy27(u/s)g(08/16)2g2m-s(p) : 48-pin usop1 (12 x 17 x 0.65 mm) - hy27(u/s)g(08/16)2g2m-s (lead) - hy27( u/s)g(08/16)2g2m -sp (lead free) rev 0.7 / nov. 2005 5 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash 1. summary description the hynix hy27(u/s)g(08/16)2g2m series is a 256mx8bit with spare 8mx8 bit capacity. the device is offered in 1.8v vcc power supply and in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is po ssible to preserve valid data while old data is erased. the device contains 2048 blocks, composed by 64 pages consisting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 60ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously in troduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all program and erase functi ons including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp# input pin. the output pin rb# (open drain buffer) sign als the status of the device during each operation. in a system with mul- tiple memories the rb# pins can be connected al l together to provide a global status signal. even the write-intensive systems can take advantage of th e hy27(u/s)g(08/16)2g2m extended reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip could be offered with the ce# don?t care function. this opti on allows the direct download of the code from the nand flash memory device by a microcontrol ler, since the ce# transitions do not stop the read opera- tion. the copy back function allows the opti mization of defective blocks management : when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data re gister is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemented. this feature allo ws to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra featur es like otp/unique id area, automatic read at power up, read id2 extension. the hynix hy27(u/s)g(08/16)2g2m series is availabl e in 48 - tsop1 12 x 20 mm , 48 - usop1 12 x 17 mm. 1.1 product list part number orization vcc range package hy27sg082g2m x8 1.70 - 1.95 volt 48tsop1 / 48usop1 hy27sg162g2m x16 hy27ug082g2m x8 2.7v - 3.6 volt hy27ug162g2m x16 rev 0.7 / nov. 2005 6 hy27ug(08/16)2g2m series hy27sg(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash figure1: logic diagram 9 & |